1. Field
This disclosure relates generally to phase locked loops, and more specifically, to a phase locked loop having a fractional voltage controlled oscillator (VCO) modulation.
2. Related Art
A radio frequency (RF) transceiver may be integrated in a system-on-a-chip (SoC) with an embedded controller or processor and other peripherals. The SoC may be for use in smart home, life, sensors, etc. in a market segment sometimes referred to as the internet of things (IOTs). There are a variety of transmitter and receiver architectures for use in an RF transceiver. The RF transceiver may include a PLL. Also, operation of the transceiver may require that the PLL be modulated. One technique for modulating the PLL is commonly known as dual port modulation. In dual port modulation, the input signal is split into a low port modulation and a high port modulation. The low port modulation is provided to a loop filter of the PLL and the high port modulation is applied to a bank of varactors used in a VCO tank circuit. The bank of varactors may be realized as a bank of finely quantized digitally switchable capacitors (varactors), or as a varactor that is controlled by a digital-to-analog converter (DAC).
The bank of varactors may include a plurality of same sized switchable capacitors. Also, the bank of varactors may include a plurality of different sized switchable capacitors, where the size of each of the capacitors corresponds to a bit position of the capacitor. In addition, varactors may include a combination of same sized and different sized switchable capacitors. Hybrid/segmented banks of varactors can be used as well. The amplitude of the high port modulation may be scaled for a least significant bit (LSB) sized varactor. To achieve finer modulation fidelity for the high port modulation, fractional modulation techniques using sigma-delta modulators to control the LSB sized varactors. However, conventional techniques for controlling multiple varactors can result in size mismatch, delay mismatch, and rise-fall timing skew between multiple sigma-delta modulation tuning bits. Also, low power, low cost, connectivity standards such as Bluetooth LE, ANT, and custom FSK/GFSK, GMSK modes do not impose modulation data whitening requirements that potentially may result in a transmission of a long sequence of ones and zeros. For a PLL high port sigma-delta modulator that executes on an interpolated frequency, this implies a DC stimulus for an extended period of time, resulting in idle tones at the sigma-delta modulator's output that causes undesirable modulated RF output/spurs. Therefore, a need exists for a PLL that solves the above problems.